CMOS image sensors are increasingly being used as low cost imaging devices. A CMOS image sensor circuit includes a focal plane array of pixel cells, each one of the cells includes a photogate, photoconductor, or photodiode having an associated charge accumulation region within a substrate for accumulating photo-generated charge. Each pixel cell may include a transistor for transferring charge from the charge accumulation region to a sensing node, and a transistor, for resetting the sensing node to a predetermined charge level prior to charge transference. The pixel cell may also include a source follower transistor for receiving and amplifying charge from the sensing node and an access transistor for controlling the readout of the cell contents from the source follower transistor.
In a CMOS image sensor, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the sensing node accompanied by charge amplification; (4) resetting the sensing node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge from the sensing node.
CMOS image sensors of the type discussed above are generally known as discussed, for example, in Nixon et al., “256 ×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994). See also U.S. Pat. Nos. 6,177,333 and 6,204,524, which describe the operation of conventional CMOS image sensors and are assigned to Micron Technology, Inc., the contents of which are incorporated herein by reference.
A schematic diagram of a conventional CMOS pixel cell 10 is shown in FIG. 1. The illustrated CMOS pixel cell 10 is a four transistor (4T) cell. The CMOS pixel cell 10 generally comprises a photo-conversion device 23 for generating and collecting charge generated by light incident on the pixel cell 10, and a transfer transistor 17 for transferring photoelectric charges from the photo-conversion device 23 to a sensing node, typically a floating diffusion region 5. The floating diffusion region 5 is electrically connected to the gate of an output source follower transistor 19. The pixel cell 10 also includes a reset transistor 16 for resetting the floating diffusion region 5 to a predetermined voltage; and a row select transistor 18 for outputting a signal from the source follower transistor 19 to an output terminal in response to an address signal.
FIG. 2 is a cross-sectional view of a portion of the pixel cell 10 of FIG. 1 showing the photo-conversion device 23, transfer transistor 17 and reset transistor 16. The exemplary CMOS pixel cell 10 has a photo-conversion device 23 may be formed as a pinned photodiode. The photodiode 23 has a p-n-p construction comprising a p-type surface layer 22 and an n-type photodiode region 21 within a p-type active layer 11. The photodiode 23 is adjacent to and partially underneath the transfer transistor 17. The reset transistor 16 is on a side of the transfer transistor 17 opposite the photodiode 23. As shown in FIG. 2, the reset transistor 16 includes a source/drain region 2. The floating diffusion region 5 is between the transfer and reset transistors 17, 16.
In the CMOS pixel cell 10 depicted in FIGS. 1 and 2, electrons are generated by light incident on the photo-conversion device 23 and are stored in the n-type photodiode region 21. These charges are transferred to the floating diffusion region 5 by the transfer transistor 17 when the transfer transistor 17 is activated. The source follower transistor 19 produces an output signal from the transferred charges. A maximum output signal is proportional to the number of electrons extracted from the n-type photodiode region 21.
Conventionally, a shallow trench isolation (STI) region 3 adjacent to the charge collection region 21 is used to isolate the pixel cell 10 from other pixel cells and devices of the image sensor. The STI region 3 is typically formed using a conventional STI process. The STI region 3 is typically lined with an oxide liner 38 and filled with a dielectric material 37. Also, the STI region 3 can include a nitride liner 39. The nitride liner 39 provides several benefits, including improved corner rounding near the STI region 3 corners, reduced stress adjacent the STI region 3, and reduced leakage for the transfer transistor 17.
The trench isolation region 3 is typically formed using a conventional STI process. The STI region 3 is formed to a depth between 2000 Angstroms (Å) and 6000 Å. The sidewalls 9 of the STI region 3 are formed at an angle θ1, which is typically between 85 degrees and 90 degrees. The STI region 3 is typically filled with a dielectric material and can include a nitride liner (not shown).
A common problem associated with the above described STI region 3 is dangling bonds (e.g., dangling silicon (Si—) bonds) at the surface of the substrate 11 and along the trench bottom 8 and sidewalls 9. The dangling bonds create a high density of trap sites along the trench bottom 8 and sidewalls 9. As a result of these trap sites formed along the bottom 8 and sidewalls 9 of the STI region 3, current generation near and along the trench bottom 8 and sidewalls 9 can be significant. Current generated from trap sites inside or near the photodiode 23 depletion region causes undesired dark current and increased fixed pattern noise.
Additionally, while the nitride liner 39 provides certain benefits, it also has undesirable effects. The portion of the transfer transistor 17 gate that overlaps the STI region 3 (not shown) can undesirably act as a second transistor with a threshold voltage “field Vt” causing current leakage. Without the nitride liner 39, the field Vt is typically approximately 15 volts (V), which is sufficiently high to minimize leakage. With the nitride liner 39, as shown in FIG. 2, the field Vt is lowered, causing increased leakage. It is believed that the decreased field Vt is due to fixed charge or surface states from the nitride liner 39.
Further, for proper operation of the pinned photodiode 23, the p-type surface implant region 22 must be continuously to the p-type substrate 11. FIG. 2 illustrates this as link region 25. Accordingly, a continuous p-type region from p-type surface layer 22 through link region 25 to the p-type substrate 11 must be established for the pinned photodiode 23 to work properly. In situations where this does not occur, e.g., where the link region 25 becomes depleted, the p-type surface region 22 becomes isolated from the p-type substrate 11 and results in a floating p-type surface region 22 rather a pinned region 22. This results in a dramatic capacitance loss in the pinned photodiode 23 and therefore, decreased image sensor performance.
It is desirable to have an improved isolation structure for reducing dark current and fixed pattern noise. It is also desirable to have an isolation structure that allows a better connection between the p-type surface region of a pinned photodiode and the substrate.